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cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-09201 rev. *c revised june 26, 2017 MB39C006A 1 ch dc/dc converter ic with pfm/pwm synchronous rectification description the MB39C006A is a current mode type 1-channel dc/dc converter ic built-in sw itching fet, synchronous rectification, and down conversion support. the device is integrat ed with a switching fet, o scillator, error amplifier, pf m/pwm control circuit, refere nce voltage source, and powergood circuit. external inductor and decoup ling capacitor are needed onl y for the external component. MB39C006A is small, achieve a highly effectiv e dc/dc converter in the full lo ad range, this is suitable as the built-in power s upply for handheld equipment such as mo bile phone/pda, dvds, and hdds. features high efficiency : 96 % (max) low current consumption : 30 a (at pfm) output current (dc/dc) : 800 ma (max) input voltage range : 2.5 v to 5.5 v operating frequency : 2.0/3.2 mhz (typ) built-in pwm operation fixed function no flyback diode needed low dropout operation : for 100 % on duty built-in high-precision refere nce voltage generator : 1.20 v 2 % consumption current in shutdo wn mode : 1 a or less built-in switching fet : p-ch mos 0.3 ? (typ) n-ch mos 0.2 ? (typ) high speed for input and load tran sient response in the current mode over temperature protection packaged in a compact package : son10 applications flash roms mp3 players electronic dictionary devices surveillance cameras portable gps navigators mobile phones etc.
document number: 002-09201 rev. *c page 2 of 36 MB39C006A contents description ................... ........................... ....................... ........................ ...................... ......................... ........................ 1 features ....................... ........................ ........................ ....................... ........................ .......................... ........................ 1 applications ............... .......................... .......................... ........................ ....................... ........................ ........................ 1 contents ..................... .......................... ........................ ....................... ........................ .......................... ........................ 2 1. pin assignment ................. ........................ ....................... ........................ .................... ...................... ..................... 3 2. pin descriptions .................. ........................ ........................ ..................... ................... ....................... ..................... 3 3. i/o pin equivalent circuit diag ram ......................... ..................... ..................... ..................... ................... ............. 4 4. block diagram ..................... ........................ ........................ ..................... ................... ....................... ..................... 5 5. function of each block ...... ........................ ........................ ....................... ....................... .................... .................. 6 6. absolute maximum ratings ..... ....................... ........................ ........................ ...................... ................. ................ 8 7. recommended operating conditions ............................ ..................... ..................... .................... ......................... 9 8. electrical characteristics ... ........................ ........................ ....................... ...................... ..................... ................ 10 9. test circuit for measuri ng typical operating characteristics ....... ............................ ........................... ........... 12 10. application notes .............. ........................ ........................ ..................... ..................... ........................ ................ 13 10.1 selection of components ........ ........................ ....................... ..................... ..................... ................... ........... 13 10.2 output voltage setting ......... ........................ ........................ ..................... .................... ................... .............. 13 10.3 about conversion efficiency ... ........................ ....................... ........................ ................... ............................. 14 10.4 power dissipation and heat considerations ............ ....................... ........................ .................... .................... 15 10.5 transient response ............. ........................ ........................ ..................... .................... ................... .............. 15 10.6 board layout, design example ........................ ....................... ........................ ..................... ........................... 15 11. example of standard operation characteristics ....... .......................... ....................... .................... .................. 17 12. application circuit examples .. ...................... ........................ ........................ ..................... .................. .............. 31 13. usage precautions ............... ........................ ....................... ..................... ..................... ...................... ................ 33 14. ordering information ........ ........................ ........................ ....................... ...................... ..................... ................ 33 15. rohs compliance information ... ........................ ....................... ........................ .................... ............................ 33 16. package dimension ................ ....................... ........................ ..................... .................... .................... ................ 34 document history .................... ........................ ........................ ..................... ..................... ........................ ................ 35 sales, solutions, and legal inform ation ........................ ..................... ..................... ..................... ........................... 36
document number: 002-09201 rev. *c page 3 of 36 MB39C006A 1. pin assignment 2. pin descriptions pin no pin name i/o description 1 lx o inductor connection output pin. high impedance during shut down. 2gnd ? ground pin. 3 ctl i control input pin. (l : shut down / h : normal operation) 4 vref o reference voltage output pin. 5 powergood o powergood circuit output pin. interna lly connected to an n-ch mos open drain circuit. 6 fsel i frequency switch pin. (l (open) : 2.0 mhz, h : 3.2 mhz) 7 vrefin i error amplifier (error amp) non-inverted input pin. 8modei operation mode switch pin. (l : pfm/pwm mode, open : pwm mode) 9 out i output voltage feedback pin. 10 vdd ? power supply pin. (top view) (wnk010) powergood vref ctl gnd lx vdd out mode vrefin fsel 12345 109876
document number: 002-09201 rev. *c page 4 of 36 MB39C006A 3. i / o pin equivalent circuit diagram ? ? gnd vdd gnd vdd lx vref power good ? gnd fsel ? gnd vdd ? gnd vdd ctl gnd vdd ? ? vrefin out ? ? ? mode * gnd vdd * * : esd protection device
document number: 002-09201 rev. *c page 5 of 36 MB39C006A 4. block diagram current mode ? original voltage mode type: stabilize the output voltage by compar ing two items below and on-duty control. ? voltage (v c ) obtained through negative feedback of the output voltage by error amp ? reference triangular wave (v tri ) ? current mode type: instead of the triangular wave (v tri ), the voltage (v idet ) obtained through i-v conversion of t he sum of currents that flow in the oscillator (rectangular wave generat ion circuit) and sw fet is used. stabilize the output voltage by compar ing two items below and on-duty control. vdd 3 error amp i out comparator 1.20 v v ref pfm/pwm logic control on/off ctl out powergood power- good vref vrefin dac mode fsel gnd lx v out vdd v in 10 3 9 5 4 7 8 ? + 6 2 1 mode control lo : pfm/pwm open : pwm
document number: 002-09201 rev. *c page 6 of 36 MB39C006A ? voltage (v c ) obtained through negative feedback of the output voltage by error amp ? voltage (v idet ) obtained through i-v conversion of th e sum of current that flow in the o scillator (rectangula r wave generation circuit) and sw fet 5. function of each block pfm/pwm logic control circuit in normal operation, frequency (2 .0 mhz/3.2 mhz) which is set by the built-in oscillat or (square wave osci llation circuit) cont rols the built-in p-ch mos fet and n-ch mos fet for the synchronous rectification operation. in the light load mode , the intermittent (p fm) operation is executed. this circuit protects against pass-through current caused by synchronous rectificati on and against reverse current caused in a non- successive operation mode. i out comparator circuit this circuit detects the current (i lx ) which flows to the external inducto r from the built-in p-ch mos fet. by comparing v idet obtained through i-v conv ersion of peak current i pk of i lx with the error amp output, th e built-in p-ch mos fet is turned off via the pfm/pw m logic control circuit. error amp phase compensation circuit this circuit compares the output voltage to reference voltages such as vref. the MB39C006A has a built-in phase compensation circuit that is designed to optimize the oper ation of the MB39C006A. this needs neither to be considered nor addition of a pha se compensation circuit and an exte rnal phase compensation device. vref circuit a high accuracy reference voltage is gener ated with bgr (bandgap reference) circui t. the output voltage is 1.20 v (typ). powergood circuit the powergood circuit monitors the voltage at the out pin. the powergood pin is op en drain output. use the pin with pull- up using the external resistor in the normal operation. when the ctl is at the h level, the powergood pin becomes the h level. however, if the output voltage drops because of over current and etc, the powergood pin becomes the l level. v in ton toff v tri v c vc v tri v in toff vc vc v idet s r ton sr-ff v idet q voltage mode type model current mode type model oscillator note : the above models illustrate th e general operation and an actual operation will be preferred in the ic.
document number: 002-09201 rev. *c page 7 of 36 MB39C006A timing chart example : (power good pin pulled up to vin) protection circuit the MB39C006A has a built-in ove r-temperature protection circuit. the over-temperature protection circuit turn s off both n-ch and p-ch switching fets wh en the junction temperature reaches +135 c. when the junction temperature drops to + 110 c, the switching fet return s to the normal operation. since the pfm/pwm control circuit of the mb 39c006a is in the control method in curr ent mode, the current peak value is also monitored and contro lled as required. function table * : don't care mode input output switching frequency ctl mode fsel output pin voltage vref powergood shutdown mode ? l * * output stop output stop function stop pfm/pwm mode 2.0 mhz h l l vout voltage output 1.2 v operation pwm fixed mode 2.0 mhz h open l vout voltage output 1.2 v operation pfm/pwm mode 3.2 mhz h l h vout voltage output 1.2 v operation pwm fixed mode 3.2 mhz h open h vout voltage output 1.2 v operation vin ctl t dlypg or less t dlypg t dlypg vout powergood v uvlo v out 97 % ( )
document number: 002-09201 rev. *c page 8 of 36 MB39C006A 6. absolute maximum ratings *1 : see ? example of standard operation characteristics ? power dissipation vs. operating ambi ent temperature? for the package power dissipation of ta from + 25 c to + 85 c. *2 : when mounted on a four- layer epoxy board of 11.7 cm 8.4 cm *3 : ic is mounted on a four-layer epoxy board, which has thermal via, and the ic's thermal pad is connected to the epoxy board (thermal via is 4 holes). *4 : ic is mounted on a four-lay er epoxy board, which has no t hermal via, and the ic's thermal pad is connected to the epoxy bo ard. notes: the use of negative voltages below ? 0.3 v to the gnd pin may create parasitic trans istors on lsi lines, which can cause abnormal operation. this device can be damaged if the lx pin is short-circuited to vdd pin or gnd pin. take measures not to keep the fsel pin fa lling below the gnd pin potential of the mb 39c006a as much as possible. in addition to erroneous operation, the ic may latch up and destroy itself if 110 ma or more current flows from this pin. warning: semiconductor devices can be permanently dam aged by application of st ress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol condition rating unit min max power supply voltage v dd vdd pin ? 0.3 + 6.0 v signal input voltage v isig out pin ? 0.3 v dd + 0.3 v ctl, mode, fsel pins ? 0.3 v dd + 0.3 vrefin pin ? 0.3 v dd + 0.3 powergood pull-up voltage v ipg powergood pin ? 0.3 + 6.0 v lx voltage v lx lx pin ? 0.3 v dd + 0.3 v lx peak current i pk the upper limit value of i lx ? 1.8 a power dissipation p d ta + 25 c ? 2632* 1, * 2, * 3 mw ? 980* 1, * 2, * 4 ta = + 85 c ? 1053* 1, * 2, * 3 mw ? 392* 1, * 2, * 4 operating ambient temperature ta ? ? 40 + 85 c storage temperature t stg ? ? 55 + 125 c
document number: 002-09201 rev. *c page 9 of 36 MB39C006A 7. recommended operating conditions note : the output current from th is device has a situation to decr ease if the power supply voltage (v in ) and the dc/dc converter output voltage (v out ) differ only by a small amount. this is a result of slope compen sation and will not damage this device. warning: the recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. all of the device's electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within th eir recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operati ng conditions, or combinat ions not represented on the data sheet. users considering application outside th e listed conditions are advised to contact their representatives beforehand. parameter symbol condition value unit min typ max power supply voltage v dd ? 2.5 3.7 5.5 v vrefin voltage v refin ? 0.15 ? 1.20 v ctl voltage v ctl ? 0 ? 5.0 v lx current i lx ??? 800 ma powergood current i pg ??? 1ma vref output current i rout 2.5 v v dd 3.0 v ?? 0.5 ma 3.0 v v dd 5.5 v ?? 1 inductor value l f osc1 = 2.0 mhz (fsel = l) ? 2.2 ? h f osc2 = 3.2 mhz (fsel = h) ? 1.5 ?
document number: 002-09201 rev. *c page 10 of 36 MB39C006A 8. electrical characteristics (ta = + 25 c, vdd = 3.7 v, vout setting value = 2.5 v, mode = 0 v) * : this value isn't be specified. this should be us ed as a reference to suppo rt designing the circuits. parameter symbol pin no. condition value unit min typ max dc / dc converter block input current i refin m 7 v refin = 0.833 v ? 100 0 + 100 na i refin lv refin = 0.15 v ? 100 0 + 100 na i refin hv refin = 1.20 v ? 100 0 + 100 na output voltage v out 9 v refin = 0.833 v, out = ? 100 ma 2.45 2.50 2.55 v input stability line 2.5 v v dd 5.5 v * 1 ? 10 ? mv load stability load ? 100 ma out ? 800 ma ? 10 ? mv out pin input impedance r out out = 2.0 v 0.6 1.0 1.5 m lx peak current i pk 1 output shorted to gnd 0.9 1.2 1.7 a pfm/pwm switch current i msw fsel = 0 v, l = 2.2 h ? 30 ? ma oscillation frequency f osc1 fsel = 0 v 1.6 2.0 2.4 mhz f osc2 fsel = 3.7 v 2.56 3.20 3.84 mhz rise delay time t pg 3, 9 c1 = 4.7 f, out = 0 a, vout = 90% ? 45 80 s sw nmos fet off voltage v noff 1 ??? 20* ? mv sw pmos fet on resistance r onp lx = ? 100 ma ? 0.30 0.47 sw nmos fet on resistance r onn lx = ? 100 ma ? 0.20 0.36 lx leak current i leak m0 lx v dd * 2 ? 1.0 ? + 8.0 a i leak hv dd = 5.5 v, 0 lx v dd * 2 ? 2.0 ? + 16.0 a protection circuit block over temperature protection (junction temp.) t otph ?? + 120* + 135* + 155* c t otpl + 95* + 110* + 130* c uvlo threshold voltage v thh 10 ? 2.07 2.20 2.33 v v thl 1.92 2.05 2.18 v uvlo hysteresis width v hys ? 0.08 0.15 0.25 v
document number: 002-09201 rev. *c page 11 of 36 MB39C006A (ta = + 25 c, vdd = 3.7 v, vout setting value = 2.5 v, mode = 0 v) *1 : the minimum value of v dd is the 2.5 v or v out setting value + 0.6 v, whichever is higher. *2 : the + leak at the lx pin includes th e current of the internal circuit. *3 : detected with respect to the output voltage setting value of v refin *4 : current consumption based on 100 % on-duty (high side fet in full on state). the sw fet gate drive current is not included because the device is in full on state (no switching operation). also the load current is not included. parameter symbol pin no. condition value unit min typ max power- good block powergood threshold voltage v thpg 5 *3 v refin 3 0.93 v refin 3 0.97 v refin 3 0.99 v powergood delay time t dlypg1 fsel = 0 v ? 250 ? s t dlypg2 fsel = 3.7 v ? 170 ? s powergood output voltage v ol powergood = 250 a ?? 0.1 v powergood output current i oh powergood = 5.5 v ?? 1.0 a control block ctl threshold volt- age v thhct 3 ? 0.55 0.95 1.45 v v thlct ? 0.40 0.80 1.30 v ctl pin input current i ictl ctl = 3.7 v ?? 1.0 a mode threshold voltage v thmmd 8 open setting ? 1.5 ? v v thlmd ? ?? 0.4 v mode pin input current i lmd mode = 0 v ? 0.8 ? 0.4 ? a fsel threshold voltage v thhfs 6 ? 2.96 ?? v v thlfs ??? 0.74 v reference voltage block vref voltage v ref 4 vref = ? 2.7 a, out = ? 100 ma 1.176 1.200 1.224 v vref load stability l oadref vref = ? 1.0 ma ?? 20 mv general shut down power supply current i vdd1 10 ctl = 0 v, all circuits in off state ?? 1.0 a i vdd1h ctl = 0 v, vdd = 5.5 v ?? 1.0 a power supply current at dc/dc operation (pfm mode) i vdd2 ctl = 3.7 v, mode = 0 v, out = 0 a ? 30 48 a power supply current at dc/dc operation (pwm fixed mode) i vdd2 ctl = 3.7 v, mode = open, out = 0 a, fsel = 0 v ? 4.8 8.0 ma power-on invalid current i vdd ctl = 3.7 v, vout = 90 % * 4 ? 800 1500 a
document number: 002-09201 rev. *c page 12 of 36 MB39C006A 9. test circuit for measuring typical operating characteristics note : these components are recommended based on the operatin g tests authorized. tdk : tdk corporation ssm : susumu co., ltd koa : koa corporation component specification vendor part number remark r1 1 m koa rk73g1jttd d 1 m r3-1 r3-2 7.5 k 120 k ssm ssm rr0816-752-d rr0816-124-d at vout = 2.5 v setting r4 300 k ssm rr0816-304-d r5 1 m koa rk73g1jttd d 1 m c1 4.7 f tdk c2012jb1a475k c2 4.7 f tdk c2012jb1a475k c6 0.1 f tdk c1608jb1h104k for adjusting slow start time l1 2.2 h tdk vlf4012at-2r2m 2.0 mhz operation 1.5 h tdk vlf4012at-1r5m 3.2 mhz operation vin vout l1 1.5 h/2.2 h c1 4.7 f i out c2 4.7 f sw ctl mode vref vrefin gnd out lx vdd gnd r5 1 m v dd v dd MB39C006A power- good fsel r1 1 m r4 300 k r3-1 7.5 k r3-2 120 k sw sw c6 0.1 f 10 3 8 4 6 7 1 9 5 2 vout = vrefin 2.97
document number: 002-09201 rev. *c page 13 of 36 MB39C006A 10. application notes 10.1 selection of components selection of an external inductor basically it dose not need to design inductor. the mb39c0 06a is designed to oper ate efficiently with a 2.2 h (2.0 mhz operatio n) or 1.5 h (3.2 mhz operation) external inductor. the inductor should be rated for a saturati on current higher than the lx peak curr ent value during normal operating conditions, and should have a minimal dc resistance. (100 m ? or less is recommended.) the lx peak current value i pk is obtained by th e following formula. l : external inductor value i out : load current v in : power supply voltage v out : output setting voltage d : on- duty to be switched( = v out /v in ) fosc : switching frequency (2.0 mhz or 3.2 mhz) ex) at v in = 3.7 v, v out = 2.5 v, i out = 0.8 a, l = 2.2 h, fosc = 2.0 mhz the maximum peak current value i pk ; i/o capacitor selection ? select a low equivalent series resistance (esr) for the vdd input capacitor to su ppress dissipation fr om ripple currents. ? also select a low equivalent series resist ance (esr) for the output capacitor. the vari ation in the inductor current causes rip ple currents on the output capacitor which, in turn, causes ripple voltages an output equal to the amount of variation multiplied b y the esr value. the output capacitor value has a significant impact on the operating stabil ity of the device wh en used as a dc/dc converter. therefore, cypress generally reco mmends a 4.7 f capacitor, or a larger capacitor value c an be used if ripple voltag es are not suitable. if the v in /v out voltage difference is within 0.6 v, the use of a 10 f ou tput capacitor value is recommended. ? types of capacitors ceramic capacitors are effective for reducing the esr and afford smaller dc/dc converter circuit. howe ver, power supply functio ns as a heat generator, therefore avoid to us e capacitor with the f-temperature rating ( ? 80% to + 20%) . cypress recommends capacitors with the b-temperature rating ( 10% to 20%). normal electrolytic capacitors are no t recommended due to their high esr. tantalum capacitor will reduce esr, however, it is dangerous to use because it turns into short mode when damaged. if you insis t on using a tantalum capacitor, cypress reco mmends the type with an internal fuse. 10.2 output voltage setting the output voltage v out of the MB39C006A is defined by th e voltage input to vrefin. supply th e voltage for inputting to vrefin from an external power supply , or set the vref output by dividing it with resistors. the output voltage when the vref in voltage is set by dividing th e vref voltage with resistors is shown in the following formula . i pk = i out + v in ? v out d 1 = i out + (v in ? v out ) v out lfosc2 2 l fosc v in i pk = i out + (v in ? v out ) v out = 0.8 a + (3.7 v ? 2.5 v) 2.5 v 0.89 a 2 l fosc v in 2 2.2 h 2 mhz 3.7 v v out = 2.97 v refin , v refin = r4 v ref r3 + r4 (v ref = 1.20 v)
document number: 002-09201 rev. *c page 14 of 36 MB39C006A note : see ? application circuit examples ? for an example of this circuit. although the output voltage is de fined according to the dividing ratio of resistance, select th e resistance value so that the current flowing through the resistance does not e xceed the vref current rating (1 ma) . 10.3 about conversion efficiency the conversion efficiency can be improved by reducing the loss of the dc/dc converter circuit. the total loss (p loss ) of the dc/dc converter is r oughly divided as follows : p loss = p cont + p sw + p c p cont : control system circuit loss (the power to operate the MB39C006A, including the gate driving po wer for internal sw fets) p sw : switching loss (the loss caused during the switch of the ic's internal sw fets) p c : continuity loss (the loss caused when currents flow th rough the ic's internal sw fets and external circuits) the ic's control circuit loss (p cont ) is extremely small, severa l tens of mw* with no load. as the ic contains fets which can switch fa ster with less power, the continuity loss (p c ) is more predominant as the loss during heavy- load operation than the control circuit loss (p cont ) and switching loss (p sw ) . * : the loss in the successive operation mode . this ic suppresses the lo ss in order to execute the pfm operation in the low loa d mode (less than 100 a in no l oad mode). mode is changed by the current peak value i pk which flows into switching fet. the threshold value is about 30 ma. furthermore, the continuity loss (p c ) is divided roughly into the loss by internal sw fet on-resistance and by external inductor series resistance. p c = i out 2 (rdc + d r onp + (1 ? d) r onn ) d : switching on-duty cycle ( = v out / v in ) r onp : internal p-ch sw fet on resistance r onn : internal n-ch sw fet on resistance rdc : external inductor series resistance i out : load current the above formula indicates that it is impo rtant to reduce rdc as much as possible to improve effi ciency by selecting component s. r4 r3 vref vrefin vref vrefin MB39C006A 4 7
document number: 002-09201 rev. *c page 15 of 36 MB39C006A 10.4 power dissipation and heat considerations the ic is so efficient that no consideratio n is required in most of th e cases. however, if the ic is used at a low power supply voltage, heavy load, high output volt age, or high temperature, it requires fu rther consideration for higher efficiency. the internal loss (p) is roughly obtained from th e following formula : p = i out 2 (d r onp + (1 ? d) r onn ) d : switching on-duty cycle ( = v out / v in ) r onp : internal p-ch sw fet on resistance r onn : internal n-ch sw fet on resistance i out : output current the loss expressed by the above formula is mainly continuity lo ss. the internal loss includes the switching loss and the contro l circuit loss as well but they are so small compared to the contin uity loss they can be ignored. in the MB39C006A with r onp greater than r onn , the larger the on-duty cycle, the greater the loss. when assuming v in = 3.7 v, ta = + 70 c for example, r onp = 0.42 ? and r onn = 0.36 ? according to the graph ?mos fet on resistance vs. operating ambient temperature? . the ic's internal loss p is 144 mw at v out = 2.5 v and i out = 0.6 a. according to the graph ?power dissipation vs. operating ambi ent temperature?, the power di ssipation at an operating ambient temperature ta of + 70 c is 539 mw and the internal loss is smaller than the power dissipation. 10.5 transient response normally, i out is suddenly changed while v in and v out are maintained constant , responsiveness includin g the response time and overshoot/undershoot voltage is ch ecked. as the MB39C006A has built-in error amp with an optimized design, it shows good transi ent response characteristics. however, if ri nging upon sudden change of th e load is high due to the opera ting conditi ons, add capac itor c6 (e.g. 0.1 f). (since this capacitor c6 changes the start time, check the start waveform as well.) this action is not requir ed for dac input. 10.6 board layout, design example the board layout needs to be designed to ensure the stable operation of the MB39C006A. follow the procedure below for designing the layout. ? arrange the input capacitor (cin) as close as possible to both the vdd and gnd pins. make a through hole (th) near the pins of this capacitor if the board has planes for power and gnd. ? large ac currents flow between the MB39C006A a nd the input capacitor (cin), output capacitor (c o ), and external inductor (l). group these components as close as possible to the MB39C006A to reduce the overall loop area oc cupied by this group. also try to mount these components on the same surface and arrange wi ring without through hole wiring . use thick, short, and straigh t routes to wire the net (the layo ut by planes is recommended.). ? the feedback wiring to the out should be wired from the voltage output pi n closest to the output capacitor (c o ). the out pin is extremely sensitive and should thus be kept wired away from the lx pin of the MB39C006A as far as possible. r4 c6 r3 vref v refin vref vrefin MB39C006A 4 7
document number: 002-09201 rev. *c page 16 of 36 MB39C006A ? if applying voltage to the vrefin pin through dividing resistors, arrange the resistors so that the wiring can be kept as short as possible. also arrange them so that the g nd pin of the vrefin resistor is close to the ic's gnd pin. further, provide a gnd exclusively for the control line so that the resistor can be connected via a path that does not carry current. if installing a bypass capacitor for the vrefin, put it close to the vrefin pin. ? try to make a gnd plane on the surface to which the MB39C006A will be mounted. for efficient heat dissipation when using the son 10 package, cypress recommends providing a thermal via in th e footprint of the thermal pad. layout example of ic sw components notes for circuit design the switching operation of the MB39C006A wor ks by monitoring and controll ing the peak current which, incidentally, serves as fo rm of short-circuit protection. however, do no t leave the output short-circuited for long periods of time. if the output is short- circuited where vin < 2.9 v, the current limit value (peak current to the inductor) tends to rise. l eaving in the short-circuit state, the temp erature of the MB39C006A will continue rising and activate the thermal protection. once the thermal protection stops the outp ut, the temperature of the ic will go down and operation will resume, after which the output will repeat the starting and stopping. although this effect will not destroy the ic, the therma l exposure to the ic over prolonged hours may affect the peripherals su rrounding it. co cin vo l gnd 1 pin vin feedback line
document number: 002-09201 rev. *c page 17 of 36 MB39C006A 11. example of standard operation characteristics (shown below is an example of characteristics for connection according to test circuit for measuring typical operating characteristics .) 50 60 70 80 90 100 v in = 3.0 v v in = 4.2 v ta = +25c v out = 2.5 v fsel = l mode = l v in = 3.7 v v in = 5.0 v 1 10 100 1000 50 60 70 80 90 100 v in = 3.0 v v in = 4.2 v ta = +25c v out = 1.2 v fsel = l mode = l v in = 3.7 v v in = 5.0v 1 10 100 1000 50 60 70 80 90 100 v in = 3.0 v v in = 4.2 v ta = +25c v out = 1.8 v fsel = l mode = l v in = 3.7 v v in = 5.0 v 1 10 100 1000 0 10 20 30 40 50 60 70 80 90 100 v in = 4.2 v ta = +25c v out = 3.3 v fsel = l mode = l v in = 3.7 v v in = 5.0 v 1 10 100 1000 load current i out (ma) conversion efficiency ( % ) load current i out (ma) conversion efficiency ( % ) load current i out (ma) conversion efficiency ( % ) load current i out (ma) conversion efficiency ( % ) conversion efficiency vs. load current (2.0 mhz:pfm/pwm mode) conversion efficiency vs. load current (2.0 mhz:pfm/pwm mode) conversion efficiency vs. load current (2.0 mhz:pfm/pwm mode) conversion efficiency vs. load current (2.0 mhz:pfm/pwm mode)
document number: 002-09201 rev. *c page 18 of 36 MB39C006A 0 10 20 30 40 50 60 70 80 90 100 v in = 3.0 v v in = 4.2 v v in = 3.7 v v in = 5.0 v ta = +25c v out = 2.5 v fsel = l mode = open 1 10 100 1000 0 10 20 30 40 50 60 70 80 90 100 v in = 3.0 v v in = 4.2 v v in = 3.7 v v in = 5.0v ta = +25c v out = 1.2 v fsel = l mode = open 1 10 100 1000 0 10 20 30 40 50 60 70 80 90 100 v in = 3.0 v v in = 4.2 v v in = 3.7 v v in = 5.0 v ta = +25c v out = 1.8 v fsel = l mode = open 1 10 100 1000 0 10 20 30 40 50 60 70 80 90 100 v in = 4.2 v v in = 3.7 v v in = 5.0 v ta = +25c v out = 3.3 v fsel = l mode = open 1 10 100 1000 load current i out (ma) conversion efficiency ( % ) load current i out (ma) conversion efficiency ( % ) load current i out (ma) conversion efficiency ( % ) load current i out (ma) conversion efficiency ( % ) conversion efficiency vs. load current (2.0 mhz:pwm fixed mode) conversion efficiency vs. load current (2.0 mhz:pwm fixed mode) conversion efficiency vs. load current (2.0 mhz:pwm fixed mode) conversion efficiency vs. load current (2.0 mhz:pwm fixed mode)
document number: 002-09201 rev. *c page 19 of 36 MB39C006A 50 60 70 80 90 100 v in = 3.0 v v in = 4.2 v v in = 3.7 v v in = 5.0 v ta = +25c v out = 2.5 v fsel = h mode = l 1 10 100 1000 50 60 70 80 90 100 v in = 3.0 v v in = 4.2 v v in = 3.7 v v in = 5.0 v ta = +25c v out = 1.2 v fsel = h mode = l 1 10 100 1000 50 60 70 80 90 100 v in = 3.0 v v in = 4.2 v v in = 3.7 v v in = 5.0 v ta = +25c v out = 1.8 v fsel = h mode = l 1 10 100 1000 0 10 20 30 40 50 60 70 80 90 100 v in = 4.2 v v in = 3.7 v v in = 5.0 v ta = +25c v out = 3.3 v fsel = h mode = l 1 10 100 1000 load current i out (ma) conversion efficiency ( % ) load current i out (ma) conversion efficiency ( % ) load current i out (ma) conversion efficiency ( % ) load current i out (ma) conversion efficiency ( % ) conversion efficiency vs. load current (3.2 mhz: pfm/pwm mode) conversion efficiency vs. load current (3.2 mhz: pfm/pwm mode) conversion efficiency vs. load current (3.2 mhz:pfm/pwm mode) conversion efficiency vs. load current (3.2 mhz:pfm/pwm mode)
document number: 002-09201 rev. *c page 20 of 36 MB39C006A 0 10 20 30 40 50 60 70 80 90 100 v in = 3.0 v v in = 4.2 v v in = 3.7 v v in = 5.0 v ta = +25c v out = 2.5 v fsel = h mode = open 1 10 100 1000 0 10 20 30 40 50 60 70 80 90 100 v in = 3.0 v v in = 4.2 v v in = 3.7 v v in = 5.0 v ta = +25c v out = 1.2 v fsel = h mode = open 1 10 100 1000 0 10 20 30 40 50 60 70 80 90 100 v in = 3.0 v v in = 4.2 v v in = 3.7 v v in = 5.0 v ta = +25c v out = 1.8 v fsel = h mode = open 1 10 100 1000 0 10 20 30 40 50 60 70 80 90 100 v in = 4.2 v v in = 3.7 v v in = 5.0 v ta = +25c v out = 3.3 v fsel = h mode = open 1 10 100 1000 load current i out (ma) conversion efficiency ( % ) load current i out (ma) conversion efficiency ( % ) load current i out (ma) conversion efficiency ( % ) load current i out (ma) conversion efficiency ( % ) conversion efficiency vs. load current (3.2 mhz:pwm fixed mode) conversion efficiency vs. load current (3.2 mhz:pwm fixed mode) conversion efficiency vs. load current (3.2 mhz:pwm fixed mode) conversion efficiency vs. load current (3.2 mhz:pwm fixed mode)
document number: 002-09201 rev. *c page 21 of 36 MB39C006A 2.40 2.0 4.0 3.0 5.0 6.0 2.42 2.44 2.46 2.48 2.50 2.52 2.54 2.56 2.58 2.60 out = -100 ma out = 0 a ta = +25c v out = 2.5 v fsel = l mode = l 2.0 4.0 3.0 5.0 6.0 2.40 2.42 2.44 2.46 2.48 2.50 2.52 2.54 2.56 2.58 2.60 out = -100 ma out = 0 a ta = +25c v out = 2.5 v fsel = h mode = l 2.0 4.0 3.0 5.0 6.0 2.40 2.42 2.44 2.46 2.48 2.50 2.52 2.54 2.56 2.58 2.60 out = -100 ma out = 0 a ta = +25c v out = 2.5 v fsel = l mode = open 2.0 4.0 3.0 5.0 6.0 2.40 2.42 2.44 2.46 2.48 2.50 2.52 2.54 2.56 2.58 2.60 out = -100 ma out = 0 a ta = +25c v out = 2.5 v fsel = h mode = open input voltage v in (v) output voltage v out (v) input voltage v in (v) output voltage v out (v) input voltage v in (v) output voltage v out (v) input voltage v in (v) output voltage v out (v) output voltage vs. input voltage (2.0 mhz: pfm/pwm mode) output voltage vs. input voltage (3.2 mhz: pfm/pwm mode) output voltage vs. input voltage (2.0 mhz: pwm fixed mode) output voltage vs. input voltage (3.2 mhz: pwm fixed mode)
document number: 002-09201 rev. *c page 22 of 36 MB39C006A 2.40 2.42 2.44 2.46 2.48 2.50 2.52 2.54 2.56 2.58 2.60 0 200 400 600 800 ta = +25c v in = 3.7 v v out = 2.5 v fsel = l 0 200 400 600 800 2.40 2.42 2.44 2.46 2.48 2.50 2.52 2.54 2.56 2.58 2.60 ta = +25c v in = 3.7 v v out = 2.5 v fsel = h -50 0 +50 +100 1.10 1.12 1.14 1.16 1.18 1.20 1.22 1.24 1.26 1.28 1.30 v in = 3.7 v v out = 2.5 v out = 0 a fsel = l mode = l 2.0 3.0 4.0 5.0 6.0 1.10 1.12 1.14 1.16 1.18 1.20 1.22 1.24 1.26 1.28 1.30 ta = +25c v out = 2.5 v fsel = l mode = l out = -100 ma out = 0 a load current i out (ma) output voltage v out (v) load current i out (ma) output voltage v out (v) input voltage v in (v) reference voltage v ref (v) operating ambient temperature ta ( c) reference voltage v ref (v) output voltage vs. load current (2.0 mhz) output voltage vs. load current (3.2 mhz) reference voltage vs. input voltage (2.0 mhz: pfm/pwm mode) reference voltage vs. operating ambient temperature (2.0 mhz: pfm/pwm mode) pfm/pwm mode pwm fixed mode pfm/pwm mode pwm fixed mode
document number: 002-09201 rev. *c page 23 of 36 MB39C006A 0 5 10 15 20 25 30 35 40 45 50 ta = +25c v out = 2.5 v mode = l 2.0 3.0 4.0 5.0 6.0 2.0 3.0 4.0 5.0 6.0 0 1 2 3 4 5 6 7 8 9 10 ta = +25c v out = 2.5 v mode = open -50 0 +50 +100 0 5 10 15 20 25 30 35 40 45 50 v in = 3.7 v v out = 2.5 v mode = l -50 0 +50 +100 0 1 2 3 4 5 6 7 8 9 10 v in = 3.7 v v out = 2.5 v mode = open input current vs. input voltage (pfm/pwm mode) input current i in (ma) input current vs. operating ambient temperature (pwm fixed mode) input current i in (ma) input current vs. operating ambient temperature (pfm/pwm mode) input current i in (ma) input current vs. input voltage (pwm fixed mode) input current i in (ma) input voltage v in (v) operating ambient temperature ta ( c) operating ambient temperature ta ( c) input voltage v in (v)
document number: 002-09201 rev. *c page 24 of 36 MB39C006A 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 ta = +25c v out = 1.8 v out = -200 ma fsel = l 2.0 3.0 4.0 5.0 6.0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 ta = +25c v out = 1.8 v out = -200 ma fsel = h 2.0 3.0 4.0 5.0 6.0 -50 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 v in = 3.7 v v out = 2.5 v out = -200 ma fsel = l 0 +50 +100 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v in = 3.7 v v out = 2.5 v out = -200 ma fsel = h -50 0 +50 +100 input voltage v in (v) oscillation frequency f osc1 (mhz) input voltage v in (v) oscillation frequency f osc2 (mhz) operating ambient temperature ta ( c) oscillation frequency f osc 1 (mhz) operating ambient temperature ta ( c) oscillation frequency f osc 2 (mhz) oscillation frequency vs. input voltage (2.0 mhz) oscillation frequency vs. input voltage (3.2 mhz) oscillation frequency vs. operating ambient temperature (2.0 mhz) oscillation frequency vs. operating ambient temperature (3.2 mhz)
document number: 002-09201 rev. *c page 25 of 36 MB39C006A 0.0 0.1 0.2 0.3 0.4 0.5 0.6 p-ch n-ch ta = +25c 2.0 3.0 4.0 5.0 6.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 v in = 5.5 v v in = 3.7 v ? 50 0 +50 +100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 v in = 3.7 v v in = 5.5 v ? 50 0 +50 +100 input voltage v in (v) mos fet on resistance r on ( ) operating ambient temperature ta ( c) p-ch mos fet on resistance r onp ( ) operating ambient temperature ta ( c) n-ch mos fet on resistance r onn ( ) mos fet on resistance vs. input voltage p-ch mos fet on resistance vs. operating ambient temperature n-ch mos fet on resistance vs. operating ambient temperature
document number: 002-09201 rev. *c page 26 of 36 MB39C006A 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ta = +25c v out = 2.5 v v thhct v thlct 2.0 3.0 4.0 5.0 6.0 0 500 1000 1500 2000 2500 3000 2632 85 1053 ? 50 0 +50 +100 0 500 1000 1500 2000 2500 3000 980 85 392 ? 50 0 +50 +100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ta = +25c v out = 2.5 v v thlmd v thmmd 2.0 3.0 4.0 5.0 6.0 input voltage v in (v) mode v th (v) input voltage v in (v) ctl v th (v) mode v th vs. input voltage ctl v th vs. input voltage operating ambient temperature ta ( c) operating ambient temperature ta ( c) power dissipation p d (mw) power dissipation vs. operating ambient temperature (with thermal via) power dissipation vs. operating ambient temperature (without thermal via) power dissipation p d (mw) v thhct : circuit off on v thlct : circuit on off
document number: 002-09201 rev. *c page 27 of 36 MB39C006A switching waveforms v lx : 2.0 v/div v out : 20 mv/div (ac) i lx : 500 ma/div v in = 3.7 v, i out = ? 20 ma, v out = 2.5 v, mode = l, ta = + 25 c 1 s/div 1 2 4 v in = 3.7 v, i out = ? 800 ma, v out = 2.5 v, mode = l, ta = + 25 c i lx : 500 ma/div v lx : 2.0 v/div v out : 20 mv/div (ac) 1 s/div 1 2 4 ? pfm/pwm operation ? pwm operation
document number: 002-09201 rev. *c page 28 of 36 MB39C006A output waveforms at su dden load changes (0 a ? ? 800 ma) output waveforms at sudden load changes ( ? 20 ma ? ? 800 ma) output waveforms at sudden load changes ( ? 100 ma ? ? 800 ma) v lx : 2.0 v/div v out : 200 mv/div i out : 1 a/div v in = 3.7 v, v out = 2.5 v, mode = l, ta = + 25 c ? 800 ma 0 a 100 s/div 1 2 4 1 2 4 v lx : 2.0 v/div v out : 200 mv/div i out : 1 a/div v in = 3.7 v, v out = 2.5 v, mode = l, ta = + 25 c ? 800 ma ? 20 ma 100 s/div 2 4 v lx : 2.0 v/div v out : 200 mv/div i out : 1 a/div v in = 3.7 v, v out = 2.5 v, mode = l, ta = + 25 c ? 800 ma ? 100 ma 100 s/div 1
document number: 002-09201 rev. *c page 29 of 36 MB39C006A ctl start-up waveform v lx : 5 v/div ctl : 5 v/div i lx :1 a/div 10 s/div v out : 1 v/div v in = 3.7 v, i out = 0 a, v out = 2.5 v, mode = l, ta = + 25 c 2 4 1 3 v lx : 5 v/div ctl : 5 v/div i lx :1 a/div 10 s/div v out : 1 v/div v in = 3.7 v, i out = ? 800 ma, (3.125 ) v out = 2.5 v, mode = l, ta = + 25 c 2 4 1 3 v lx : 5 v/div ctl : 5 v/div i lx :1 a/div 10 ms/div v out : 1 v/div v in = 3.7 v, i out = 0 a, v out = 2.5 v, mode = l, ta = + 25 c 2 4 1 3 v lx : 5 v/div ctl : 5 v/div i lx :1 a/div 10 ms/div v out : 1 v/div v in = 3.7 v, i out = ? 800 ma, (3.125 ) v out = 2.5 v, mode = l, ta = + 25 c 2 4 1 3 (no load, no vrefin capacitor) (m aximum load, no vrefin capacitor) (no load, vrefin capacitor = 0.1 f) (maximum load, vrefin capacitor = 0.1 f)
document number: 002-09201 rev. *c page 30 of 36 MB39C006A ctl stop waveform (no load, vrefin capacitor = 0.1 f) current limitation waveform v lx : 5 v/div ctl : 5 v/div i lx :1 a/div 10 s/div v out : 1 v/div v in = 3.7 v, i out = ? 800 ma, (3.125 ) v out = 2.5 v, mode = l, ta = + 25 c 2 4 1 3 v out : 1 v/div 2.5 v 1.5 v 10 s/div l lx : 1 a/div 1.2 a v in = 3.7 v, i out = ? 600 ma (4.2 ) i out = ? 1.2 a (2.1 ) v out = 2.5 v, mode = l,ta = + 25 c 600 ma 1 2 4 v powergood : 1 v/div normal operation current limitation operation normal operation
document number: 002-09201 rev. *c page 31 of 36 MB39C006A waveform of dynamic output voltage transition (v o1 1.8 v ? 2.5 v) 12. application circuit examples application circuit example 1 ? an external voltage is input to the referenc e voltage external input (vrefin) , and the v out voltage is set to 2.97 times as much as the v out setting gain. v in = 3.7 v, i o1 = ? 800 ma, ? 576 ma (3.125 ), mode = l, ta = + 25 c, vrefin 1 v out : 200 mv/div v vrffin : 200 mv/div 610 mv 840 mv 3 1.8 v 10 s/div 2.5 v no, vrefin capacitor v out = 2.97 v refin v in cpu v out apli c2 c1 l1 r5 dac 4.7 f 4.7 f 2.2 h 1 m vdd ctl fsel vref vrefin gnd lx out power- good mode l ( open ) = 2.0 mhz h = 3.2 mhz 10 3 5 9 1 6 4 7 2 8 l=pfm/pwm mode open=pwm fixed mode
document number: 002-09201 rev. *c page 32 of 36 MB39C006A application circuit example 2 ? the voltage of vref pin is input to th e reference voltage external input (vre fin) by the dividing resistors. the v out voltage is set to 2.5 v. application circuit example components list tdk : tdk corporation fdk : fdk corporation koa : koa corporation component item part number specification package vendor l1 inductor vlf4012at-2r2m 2.2 h, rdc = 76 m smd tdk mipw3226d2r2m 2.2 h, rdc = 100 m smd fdk c1 ceramic capacitor c2012jb1a475k 4.7 f (10 v) 2012 tdk c2 ceramic capacitor c2012jb1a475k 4.7 f (10 v) 2012 tdk r3 resistor rk73g1jttd d 7.5 k rk73g1jttd d 120 k 7.5 k 120 k 1608 1608 koa r4 resistor rk73g1jttd d 300 k 300 k 1608 koa r5 resistor rk73g1jttd d 1 m 0.5 % 1608 koa v out = 2.97 v refin v out = 2.97 ( v ref = 1.20 v ) v refin = r4 r3 + r4 r4 300 k vdd ctl fsel vref vrefin gnd lx out power- good mode 10 3 5 9 1 6 4 7 2 l ( open ) = 2.0 mhz r3 127.5 k h = 3.2 mhz v out apli c1 l1 4.7 f 2.2 h r3(120 k + 7.5 k ) cpu r5 1 m v in c2 4.7 f v ref 1.20 v = 2.5 v 300 k 127.5 k + 300 k 8 l=pfm/pwm mode open=pwm fixed mode
document number: 002-09201 rev. *c page 33 of 36 MB39C006A 13. usage precautions 1. do not configure the ic over the maximum ratings lf the lc is used over the maximum rati ngs, the lsl may be permanently damaged. it is preferable for the device to normall y operate within the recommended usage cond itions. usage outside of these conditions can adversely affect reli ability of the lsi. 2. use the devices within recom mended operating conditions the recommended operating conditions are the conditions under which th e lsl is guaranteed to operate. the electrical ratings are guaran teed when the device is used wit hin the recommended operating co nditions and under the conditi ons stated for each item. 3. printed circuit board ground lines should be set up with consideration for common impedance 4. take appropriate static electricity measures. containers for semiconductor material s should have anti-static protection or be made of conductive material. after mounting, printed circuit boards should be stored and shipped in conductive bags or containers. work platforms, tools, and instrume nts should be properly grounded. working personnel should be grou nded with resistance of 250 k ? to 1 m ? between body and ground. 5. do not apply negative voltages. the use of negative voltages below ? 0.3 v may create parasitic tr ansistors on lsi lines, whic h can cause abnormal operation. 14. ordering information 15. rohs compliance information the lsi products of cypress with ?e1? ar e compliant with rohs direct ive, and has observed the standard of lead, cadmium, mercury, hexavalent chromium, polybr ominated biphenyls (pbb), and poly brominated diphenylethers (pbde). a product whose part number has trailing characters ?e1? is rohs compliant. part number package remarks MB39C006Apn 10-pin plastic son (wnk010) ?
document number: 002-09201 rev. *c page 34 of 36 MB39C006A 16. package dimension millimeter nom. min. b e 2.40 bsc 3.00 bsc d a 1 a 3.00 bsc 0.00 symbol max. 0.75 0.05 0.50 bsc l 0.22 0.25 0.28 e d 2 2 1.70 bsc e c 0.30 ref 0.40 0.30 0.50 2. dimensioning and tolerancinc conforms to asme y14.5-1994. 3. n is the total number of terminals. 4. dimension "b" applies to metallized terminal and is measured between 0.15 and 0.30mm from terminal tip.if the terminal has the optional radius on the other end of the terminal. the dimension "b"should not be measured in that radius area. 5. nd refer to the number of terminals on d or e side. 6. max. package warpage is 0.05mm. 1. all dimensions are in millimeters. 7. maximum allowable burrs is 0.076mm in all directions. 8. pin #1 id on top will be located within indicated zone. 9. bilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. note 10. jedec specification no. ref : n/a side view bottom view top view d a e b 0.10 c 2x 0.10 c 2x 0.10 c a a1 0.05 c c seating plane d2 e2 0.10 c a b 0.10 c a b 10 e b 0.10 c a b 0.05 c (nd-1) e index mark 8 4 5 9 l 9 6 1 5 package code: wnk010 002-15676 rev. **
document number: 002-09201 rev. *c page 35 of 36 MB39C006A document history spansion publication number: ds04-27245-2e document title: MB39C006A, 1 ch dc/dc conver ter ic with pfm/pwm synchronous rectification document number: 002-09201 revision ecn orig. of change submission date description of change ** - taoa 11/21/2008 migrated to cypress and assigned document number 002-09201. no change to document contents or format. *a 5518137 taoa 11/11/2016 updated to cypress template *b 5632018 hixt 02/15/2017 updated pin assignment : change the package name fr om lcc-10p-m04 to wnk010 updated ordering information : change the package name from lcc-10p-m04 to wnk010 deleted ?labeling sample (lead free version)? deleted ?marking format? deleted ?recommended mounting conditions of MB39C006Apn? deleted ?evaluation board specification? deleted ?ev board ordering information? updated package dimension : updated to cypress format *c 5785801 masg 06/26/2017 adapted cypress new logo.
document number: 002-09201 rev. *c revised june 26, 2017 page 36 of 36 ? cypress semiconductor corporation, 2008-2017. this document is the property of cypre ss semiconductor corporation and its subs idiaries, including spansion llc (?cypress?). this document, including any software or firmwa re included or referenced in this document (?software?), is owne d by cypress under the intellec tual property laws and treaties of th e united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patent s, copyrights, trad emarks, or other intellectual property right s. if the software is not accomp anied by a license agreement and yo u do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (witho ut the right to sublicense) (1) under its copyright rights in the software (a) for softwa re provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in bi nary code form externally to end users (either directly or indirectly through rese llers and distributors), solely for use on cy press hardware produc t units, and (2) u nder those claims of cypress?s patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import t he software solely for use with cypress hardware product s. any other use, reproduction, modi fication, translati on, or compilation of the software is prohibited. to the extent permitted by applicab le law, cypress makes no warrant y of any kind, express or implie d, with regard to this docum ent or any software or accompanying hardware, includ ing, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypr ess reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the applicati on or use of any product or circuit described in this document. any informati on provided in this document, incl uding any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this docum ent to properly design, prog ram, and test the functional ity and safety of any appli cation made of this information and any resulting product. cypress products are not designed, inte nded, or authorized for use as critical components in systems designe d or intended for the operation of w eapons, weapons systems, nuclear instal lations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management , or other uses wher e the failure of the device or system could cause per sonal injury, death, or property damage (?uninte nded uses?). a critical component is any compo nent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. cypress is not liable, in who le or in part, and you shall and hereby do release cypre ss from any claim, damage, or other liability arisi ng from or related to all unin tended uses of cypress products. you shall indemnify and hold cy press harmless from and against all claims, costs, damages, and other liabilities, including claims for pe rsonal injury or death, arising from or related to any un intended uses of cypress products. cypress, the cypress logo, spansion, the spansion l ogo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or regist ered trademarks of cypress in the united states and other countries. for a more complete li st of cypress trademar ks, visit cypress.com. other names and bra nds may be claimed as property of their respective owners.. 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